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MTC20454
QUAD INTEGRATED ADSL CMOS ANALOG FRONT END CIRCUIT

Fully integrated quad AFE for ADSL Overall 12 bit resolution 1.1MHz signal bandwidth 8.8 MS/s ADC 8.8 MS/s DAC THD: -60 dB @ full scale 1 V full scale input Differential analog I/O Accurate continuous-time channel filtering 3rd & 4th order tuneable continuous time LP Filters 100 pin TQFP package, Industrial Range qualified 175 mW power consumption per line
TQFP100 14x14x1.4 ORDERING NUMBER: MTC20454-TQ-I
fifth generation Analog Front End (AFE) designed for DMT based ADSL modems compliant with ITU G.992.1 and G.992.1 standards. It includes four 12 bit DACs and one 13 bit ADC. It is intended to be used with the MTC20455 DMT/ ATM processor as part of the MTK20450. The MTC20454 provides programmable low pass filters for each of the two channels and automatic gain control for four individual ADSL modems. The pipeline ADC architecture provides 13 bit dynamic range and a signal bandwidth of 1.1 MHz. The device consumes only 0.7 Watt in full operation of all four modems and has a power down mode for standby. It is housed in a compact 100 pin thin plastic quad flat package.
APPLICATIONS ADSL Front-end for high density, low power central office and digital loop carrier equipment DESCRIPTION
The MTC20454 is the first DynaMiTe ADSL (Asynchronous Digital Subscriber Line) analog front end designed specifically for the central office. It is a Figure 1. Sample board layout
Discrete FE
LD
Discrete FE
LD MTC20454 Quad Analog Front End
MTC20455 Quad ADSL DMT Modem and ATM Framer
Line
Discrete FE LD
ATM
Discrete FE
LD
SDRAM
MTC20136 Modem Controller
February 2004
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MTC20454
PIN DESCRIPTION
N Pin Digital Interface 1 DVSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 98 99 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 CTRLIN CLKIN DVDD DVDD CLKM CLKWD RX3 RX2 RX1 RX0 DVSS ONELINE RESETN Description Negative supply for input IOs + core Transmit data bus bit 7 (MSB) Transmit data bus bit 6 Transmit data bus bit 5 Transmit data bus bit 4 Transmit data bus bit 3 Transmit data bus bit 2 Transmit data bus bit 1 Transmit data bus bit 0 (LSB) Serial control interface input Master clock (35.328MHz) input Positive supply for input IOs + core Positive supply for output IOs Master clock output Word clock output Receive data bus bit 3 (MSB) Receive data bus bit 2 Receive data bus bit 1 Receive data bus bit 0 (LSB) Negative supply for output IOs If high: TX, RX itfce is MTC-20455 compatible General reset (active low) Test mode selection (static) ADC analog negative supply ADC analog positive supply ADC virtual ground decoupling ADC negative reference decoupling ADC positive reference decoupling DAC's voltage reference decoupling Analog general purpose control pin - Line3 DAC's analog positive supply Analog general purpose control pin - Line3 Analog general purpose control pin - Line2 Analog general purpose control pin - Line2 DAC's analog negative supply DS filters analog negative supply External TX driver shutdown - Line3 DS filters analog positive supply Internal TX pre-drivers positive supply External TX driver bias control LSB - Line3 Internal pre-drivers negative supply External TX driver bias control MSB - Line3 External TX driver shutdown - Line2 External TX driver bias control LSB - Line2 External TX driver bias control MSB - Line2 Connection Dig supply MTC-20455 MTC-20455 MTC-20455 MTC-20455 MTC-20455 MTC-20455 MTC-20455 MTC-20455 MTC-20455 System Dig supply Dig supply System System MTC-20455 MTC-20455 MTC-20455 MTC-20455 Dig supply System System Strap Ana supply Ana supply C network C network C network C network Board Ana supply Board Board Board Ana supply Ana supply TX driver Ana supply Ana supply TX driver Ana supply TX driver TX driver TX driver TX driver VSSI SCHMITTC SCHMITTC SCHMITTC SCHMITTC SCHMITTC SCHMITTC SCHMITTC SCHMITTC SCHMITTC SCHMITTC VDDI VDDE BD4SCR BT4CR BT4CR BT4CR BT4CR BT4CR VSSE SCHMITTC SCHMITTC SCHMITTC VSSI VDDI OANA OANA OANA OANA BT4CR VDDI BT4CR BT4CR BT4CR VSSI VSSI BT4CR VSSI VDDI BT4CR VSSI BT4CR BT4CR BT4CR BT4CR Type
100 TEST Analog Interface 21 AVSSADC 25 28 29 30 32 34 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AVDDADC VREF VRAN VRAP DACVREF L3GP0 AVDDDAC L3GP1 L2GP0 L2GP1 AVSSDAC AVSSDS L3DRVSD AVDDDS AVDD TXDRV L3DRV0 AVSS TXDRV L3DRV1 L2DRVSD L2DRV0 L2DRV1
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PIN DESCRIPTION (continued)
N 51 52 53 54 55 56 57 58 59 60 61 62 63 Pin L3AVSSLNA L3RXN L3RXP L3AVDDLNA L3TXN L3TXP L2AVSSLNA L2RXN L2RXP L2AVDDLNA L2TXN L2TXP L1AVSSLNA Description LNA analog negative supply - Line3 Analog RX signal negative input (diff) - Line3 Analog RX signal positive input (diff) - Line3 LNA analog positive supply - Line3 Analog TX signal negative output (diff) - Line3 Analog TX signal positive output (diff) - Line3 LNA analog negative supply - Line2 Analog RX signal negative input (diff) - Line 2 Analog RX signal positive input (diff) - Line2 LNA analog positive supply - Line 2 Connection Ana suppply RX input RX input Ana supply TX output TX output Ana supply RX input RX input Ana supply VSSI OANA OANA VDDI OANA OANA VSSI OANA OANA VDDI OANA OANA VSSI OANA OANA VDDI OANA OANA VSSI OANA OANA VDDI OANA OANA OANA BT4CR BT4CR BT4CR BT4CR VSS BT4CR VDDI VSSI BT4CR VSSI VSSI BT4CR BT4CR VDDI BT4CR BT4CR Analog Analog Analog Analog Type
Analog TX signal negative output (diff) - Line2 TX output Analog TX signal positive output (diff) - Line2 TX output LNA analog negative supply - Line1 Ana supply RX input RX input Ana supply TX output TX output Ana supply RX input RX input Ana supply TX output TX output C network TX driver TX driver TX driver TX driver Ana supply TX driver Ana supply Ana supply TX driver Ana supply Ana supply Board Board Ana supply Board Board Test Test Test Test
64 L1RXN Analog RX signal negative input (diff) - Line1 65 L1RXP Analog RX signal positive input (diff) - Line1 66 L1AVDDLNA LNA analog positive supply - Line1 67 L1TXN Analog TX signal negative output (diff) - Line1 68 L1TXP Analog TX signal positive output (diff) - Line1 69 L0AVSSLNA LNA analog negative supply - Line0 70 L0RXN Analog RX signal negative input (diff) - Line0 71 L0RXP Analog RX signal positive input (diff) - Line0 72 L0AVDDLNA LNA analog positive supply - Line0 73 L0TXN Analog TX signal negative output (diff) - Line0 74 L0TXP Analog TX signal positive output (diff) - Line0 75 VAGND Analog virtual ground 76 L1DRVSD External TX driver shutdown - Line1 77 L1DRV1 External TX driver bias control MSB - Line1 78 L1DRV0 External TX driver bias control LSB - Line1 79 L0DRVSD External TX driver shutdown - Line0 80 AVSS TXDRV Internal pre-drivers negative supply 81 L0DRV1 External TX driver bias control MSB - Line0 82 AVDD TXDRV Internal TX pre-drivers positive supply 83 AVDDDS DS filters analog positive supply 84 L0DRV0 External TX driver bias control LSB - Line0 85 AVSSDS DS filters analog negative supply 86 AVSSDAC DAC's analog negative supply 89 L1GP0 Analog general purpose control pin - Line1 90 L1GP1 Analog general purpose control pin - Line1 91 AVDDDAC DAC analog positive supply 92 L0GP0 Analog general purpose control pin - Line0 93 L0GP1 Analog general purpose control pin - Line0 Analog Test Access Interface 87 TOP Pos. diff. output test access 88 TON Neg. diff output test access 94 TIN Pos. diff input test access 95 TIP Neg. diff inp0ut test access
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Figure 2. MTC20454 Grounding and Decoupling Networks
A VDD Analog VDD 10 F 100nF (each pin must have its own capacitor)
VREP pin 10F 100nF 10F 100nF VRAP pin 10 F 100nF 100nF
VRAN pin
DACVREF pin
AGND pin
100nF
100nF
Figure 3. PIN CONNECTION
A VDDADC A VSSADC DVSS RX0 RX1 RX2 RX3 CLKWD CLKM DVDD DVDD CLKIN CTRLIN TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 DVSS
8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 26 27
VREF VRAN VRAP DACVREF L3GP0 VDDDAC A L3GP1 L2GP0 L2GP1 VSSDAC A VSSDS A L3DR VSD VDDDS A VDDTXDR V A L3DR V0 VSSTXDR V A L3DR V1 L2DR VSD L3DR V0 L2DR V1
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TEST RESETN ONELINE
TIP TIN LOGP1 LOGP0 A VDDAC LAGP1 LAGP0 TON TOP A VSSDAC A VSSDS LODR V0 A VDDDS A VDDTXDR V LODR V1 A VSSTXDR V LODR VSD LIDR V0 LIDR V1 LIDR VSD
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
VSSLNA L3A L3RXN L3RXP VDDLNA L3A
VDDLNA L3A L3TXN L3TXP VSSLNA L2A L2RXN L2RXP VDDLNA L2A L2TXN L2TXP VSSLNA L1A L1RXN LIRXP VDDLNA LIA LITXN LITXP VSSLNA LOA LORXN LDRXP VDDLNA LOA LOTXN LOTXP
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AGND V
MTC20454
ABSOLUTE MAXIMUM RATINGS Operation of the device beyond these limits may cause permanent damage. It is not implied that more than one of these conditions can be applied simultaneously.
Symbol VDD Vin Tstg TL ILU Parameter Description Any VDD supply voltage, related to substrate Voltage at any input pin Storage Temperature Lead Temperature (10 second soldering) Latch-up current @ 80C 100 Min -0.5 -0.5 -40 Max 5 VDD + 0.5 125 300 Unit Vhh V C C mA
OPERATING CONDITIONS Unless specified, the characteristic limits of `Static characteristics' in this document apply for the following operating conditions:
Symbol AVDD DVDD Vin, Vout Pd Tamb Tj Parameter Description AVDD supply voltage, related to substrate DVDD supply voltage, related to substrate Voltage at any input and output pin Power Dissipation Ambient Temperature Junction temperature Min 3.0 2.7 0 0.4 -40 -40 Max 3.6 3.6 VDD 0.6 85 110 Unit V V V W C C
ELECTRICAL CHARACTERISTICS Static Characteristics a. Digital Inputs Schmitt-trigger inputs: TXi, CTRLIN, CLKIN, RESETN, TEST Clock Driver Input
Symbol VIL VIH VH Cinp Parameter Low level input voltage High level input voltage Hysteresis Input capacitance 0.8*DVDD 1.0 1.3 3 Test Condition Min. Typ. Max. 0.2*DVDD Unit V V V pF
b. Digital Outputs Hard driven outputs: RXi, CLKWD, LiGPi, LiDRVi, LiDRVSD Clock Driver Output
Symbol VOL VOH Cload Parameters Low level output voltage High level output voltage Load capacitance Test Cond Iout = 4 mA Iout = 4 mA .85*DVDD 1.0 30 Min Max .15*DVDD Unit V V pF
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Clock Driver Output CLKM
Symbol VOL VOH Cload Dcycle Parameters Low level output voltage High level output voltage Load capacitance Duty cycle 45 Test Cond Iout = 4 mA Iout = 4 mA .85*DVDD 30 55 Min Max .15*DVDD Unit V V pF %
FUNCTIONAL DECRIPTION The MTC20454 performs the analog portions of four ATU-C modems. It has filters (with a programmable cut-off frequency) that use automatic continuous time tuning to avoid time varying phase characteristics which can be of dramatic consequence for DMT modems. It requires few external components, uses a 3.3 V supply and is packaged in a 100 pins TQFP in order to reduce PCB area. The following descriptions apply to each of the four analog front ends in the chip: The Receiver (RX) The DMT signal coming from the lines to the MTCMTC20454MTC2045420454 is first filtered by the two following external filters: POTS HP filter: Attenuation of speech and POTS signalling.
Channel filter: Attenuation of echo signal to improve RX dynamic.
The signal is amplified by a low noise gain stage (-15..+31 dB) then lowpass filtered to avoid anti-aliasing and to ease further digital processing by removing unwanted high frequency out-of-band noise. A 12 bits A/D converter samples the data at 8.832 MS/s, transforms the signal into a igital representation and sends it to the DMT signal processor via the multiplexed digital interface. The Transmitter (TX/TXE) The 12 bits data at 8.832 Ms coming from the DMT signal processor through the multiplexed digital interface are transformed by a D/A converter into an analog signal. This signal is then filtered to decrease DMT sidelobes levels and meet the ANSI transmitter spectral response but also to reduce he out-of-band noise (which can be echoed to the RX path) to an acceptable level. The pre-driver buffers The signal for the external line driver and case of short loops provide attenuation provision The Digital Interface The digital part of the MTC20454 can be divided into two parts: The data interface converts the multiplexed data from/to the DMT signal processor into a valid representation for the TX DAC and RX ADC for the requested line.
The control interface allows the board processor to configure the MTC20454 paths (RX/TX gains, filter band, ...) or settings.
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ANALOG TX/RX SIGNALS The reference impedance for all power calculations is 100 Ohm. DMT Signal A DMT signal is basically the sum of N independently QAM modulated signals, each carried over a distinct carrier. The frequency separation of each carrier is 4.3125 KHz with a total number of 256 carriers (ANSI). For a large N, the signal can be modelled by a gaussian process with a certain amplitude probability density function. Since the maximum amplitude is expected to arise very rarely, the signal is clipped to tradeoff the resulting SNR loss against AD/DA dynamic range. A clipping factor (Vpeak/Vrms = "crest factor") of 5 is used resulting in a maximum SNR of 75 dB. ADSL DMT signals are nominally sent at -40 dBm/Hz +/- 3 dB (-3.65 dBm/carrier) with a maximal power of 100 mW for downlink transmitter and 4.5 mW for uplink transmitter. The minimum SNR+D needed for DMT carrier demodulation is about (3*N+20) dB with a minimum of 38 dB where N is the constellation size of a carrier (in bits). Block Diagram The transformer has a 1:2 ratio. The termination resistors are 12.5 Ohm in case of 100 Ohm lines. The hybrid bridge resistors should be < 2.5 kOhm for low-noise. An HP filter must be used on the TX path to reduce DMT sidelobes and out-of- band noise influence on the receiver. On the RX path, a LP filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. The POTS filter is used in both directions to reduce cross talk between ADSL signals and POTS speech and signalling. Figure 4. AFE Block Diagram (for detailed schematics see MTB20450-EBC reference design.)
L0RXN L1RXN L2RXN L3RXN A= -15...0dB, 5dB step G= 0...31dB, 1dB step L0RXP L1RXP L2RXP L3RXP + Tuning circuit L/V - Ref Digital ifce CTRL/TST ifce DAC + L3TXP L3AGCtx L3TXN A= -15...0dB, 5dB step G= 0...31dB, 1dB step L3AGCtx
A= -15...0dB, 5dB step G= 0...31dB, 1dB step
L0AGCrx L0AACrx
+
+ -
L1AGCrx L1AACrx
A= -15...0dB, 5dB step G= 0...31dB, 1dB step
+
+ -
L2AGCrx L2AACrx
+
+ -
L3AGCrx L3AACrx
+
276kHz AAF
276kHz AAF
276kHz AAF
276kHz AAF
ADC
DAC
DAC
DAC
1.1 mHz HCDS
1.1 mHz HCDS
1.1 mHz HCDS
1.1 mHz HCDS
G= -9...6dB, 1dB step
G= -9...6dB, 1dB step
G= -9...6dB, 1dB step
+ -
+
L0AGCtx
+ -
+
L1AGCtx
+ -
+
G= -9...6dB, 1dB step
L2AGCtx
+ -
L0TXN
L1TXN
L2TXN
L0TXP
L1TXP
L2TXP
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MTC20454RX PATH Speech Filter An external bi-directional LP filter for up and downstream POTS service splits out the speech signal to the analog telephone. The ADSL analog front end integrated circuit does not contain any circuitry for the POTS service but guarantees that the POTS bandwidth is not disturbed by spurious signals from the ADSL spectrum. Channel Filters The purpose of these external analog circuits is to provide partial echo cancellation by analog filtering of the receive. This is feasible because the upstream and the downstream data can be modulated on separate carriers (FDM). Signal Attenuator (ATT) and Low Noise Amplifier The attenuator needs to be DC decoupled from the external circuitry. In fact, it is also used to internally fix the LNA input common mode voltage at the nominal value: AVDD/2. This is done by the use of an internal biasing circuit. It is therefore mandatory to de-couple the MTC20454 input from any external DC biasing system. The Low Noise Amplifier (LNA) placed after the ATT will be used in combination with the attenuation block. The goal is to obtain a range of RX path input level varying from -15 dB to 31 dB, while maintaining the noise contribution negligible. RX Filters The combination of the external filter (an LC ladder filter typically) with the integrated low pass filter provides: echo reduction to improve dynamic Range - DMT sidelobe and out of band (anti-aliasing) attenuation.
Anti alias filter (60 dB rejection @ image freq.)
Linearity of RX Linearity of the RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5 Vpd amplitude (total _1 Vpd) at the output of the RX-AGC amplifier (i.e: before the ADC) for the case of minimal AGC setting. Figure 5. Signal Attenuator (ATT) and Low Noise Amplifier
Attenuation 2 RXP
Gain 5 V ref
LNA
RXN Attenuator
MTC 20454
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Power Supply Rejection The noise on the power supplies for the RX-path must be lower than 50 mVrms in-band white noise for any AVDD. The pre-driver drives an external line power amplifier which transmits the required power to the line. TX Filter The TX filters act not only to suppress the DMT sidebands but also as smoothing filters on the D/A converter's output to suppress the image spectrum. For this reason they are realised in a time continuous approach. ATU-C-TX Filter Same filter as ATU-R-RX. Its purpose is now is to remove image frequency of the transmitted signal according the ANSI definition. Linearity of TX Linearity of the TX is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.25 Vpd amplitude (-6 dB FS) at the output of the pre-driver for the case of a total AGC = 0 dB. Power Supply Rejection The noise on the power supplies for the TX-path must be lower than the following: < 50 mVrms in band white noise for AVDD.
< 15 mVrms in band white noise for Pre-driver AVDD.
Figure 6. Power Supply Rejection
TX Pre-driver Capability
dB
-40 -50 -60 -70 1k 10k 100k1M 10M Hz
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DIGITAL INTERFACE Control Interface The digital code setting for the MTC20454 configuration is sent over a serial line (CTRLIN) using the word clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit (`0'), the three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are latched but they are overruled by the normal settings if the TEST pin is low. Control Interface Timing The control interface bits are considered valid on each positive edge of the master clock (CLKM). They will be sampled at this moment. The stop bit will trigger the internal data validation. The timing requirements are depicted in the following figure and table: Table 1. Control interface timing requirements
Symbol Ts Th Tdv Parameter Setup time Hold time Data valid Min 0.5 ns 0.2 ns 0.5 ns Typ Max 4 ns Remarks
Figure 7. Control interface chronodiagram
CLKM CLKWD Tdv CTRLIN Start bit Th Ts ctrl cmd bits 1 stop bit (high)
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Receive / Transmit Interface The digital interface is based on a 4 * 8.832 MHz (35.328 MHz) clock. The 8.832MHz 12 bits A/D output signal or the D/A input signal are SIPO multiplexed over 4 parallel 35.328MHz data lines in the following table. If OSR = 2 bit is selected, CLKNIB is used as nibble clock (17.664 MHz, disabled in normal mode), and all the Table 2. RXi, TXi, CLKWD periods are twice
Packet Number Packet 1 Bus Line RX0/TX0 RX1/TX1 RX2/TX2 RX3/TX3 Packet 2 RX0/TX0 RX1/TX1 RX2/TX2 RX3/TX3 Packet 3 RX0/TX0 RX1/TX1 RX2/TX2 RX3/TX3 Packet 4 RX0/TX0 RX1/TX1 RX2/TX2 RX3/TX3 Word bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
TX / TXE Signal Dynamic Range The dynamic range of the signal for both DACs is 12 bits extracted from the available signed 16 bit representation coming from the digital processor. The maximal positive number is 2 11 -1, the most negative number is -2 11, the 3 least significant bits are ignored. Any signal exceeding these limits is clamped to the maximal value. Table 3. TX bit map
Sign Sign B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 n.u n.u n.u
RX Signal Dynamic Range The dynamic range of the signal from the ADC is limited to 13 bits. hose bits are converted to a signed representation with a maximal positive number of 2 12 -1 and a most negative number of -2 12. The 2 LSBs are filled with `0'. Table 4. RX bit map in normal mode
Sign B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0
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Receive / Transmit Interface Timing This interface is a triple (RX,TX, TXE) nibble-serial interface running at 8.8 MHz sampling (normal mode). The data are represented in 16 bits format, and transferred in groups of 4 bits (nibbles). The LSBs are transferred first. The MTC20454 generates a nibble clock (= master clock in normal mode, CLKNIB in OSR = 2 mode) and word signals shared by the three interfaces. Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going edge of CLKM/CLKNIB. This holds for the data stream from MTC20454 and rom the digital processor. Data, CLWD set-up and hold times are 5 ns with reference to the falling edge of CLKM/CLKNIB. RXD is sampled with CLKM rising edge. Figure 8. TX/RX Digital Interface Timing
CLKM 35.328Mhz CLKWD 8.832Mhz Tdv Ts Th TXDx Tdv RXDx N0 N1 N2 N3
Table 5. TX/RX Digital Interface timing
Symbol Ts Th Tdv Parameter Setup time Hold time Data valid Min 0.5 ns 0.2 ns 0.5 ns Typ Max 4 ns
Reset Function The MTC20454 is placed in reset mode when the RESETN pin is pulled to ground (active low signal). The chip status is depicted in the following table:
Reset CLKM pin is replicating the CLKIN input clock. System clock available CLKWD is not generated. The pin stays at high level Digital blocks are in reset: no activity Analog blocks are in powerdown External driver is forced to powerdown
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Test Four different test modes are implemented. The functional test mode allows separate access to different analog parts of the circuit in order to check some characteristics. Various test configurations are available via the CTRLIN interface. The digital core scan and the I/O nand tree test modes are dedicated for the detection of hardware process flaws in digital elements and IOs. The last test mode allows to put the outputs in the tristate mode in order to be able to perform the ESD qualification tests. Test is enabled with a high level n the TEST pin. The actual value of TX1 and TX0 bits on the rising edge of the TEST pin will set the test mode. The available test modes and their corresponding signal values are summarized in the following table: Table 6. Tests mode accessMTC20454
TX1 0 0 1 1 TX0 0 1 0 1 Test Mode functional test (enable various tests accesses via CTRLIN interface digital scan chain test I/O nand tree Tristate output for ESD
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mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K ccc 0.45 0.05 1.35 0.17 0.09 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.60 1.00 0.75 0.018 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.003 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011 0.008 0.630 0.551 0.472 0.020 0.630 0.551 0.472 0.024 0.039 0.030
OUTLINE AND MECHANICAL DATA
0 (min.), 3.5 (typ.), 7(max.) 0.080 0.003
TQFP100 (14x14x1.40mm)
0086901 C
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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